Silicon Canvas Laker 301v4 (版图设计系统)
软件简介—SoftWare Description: Silicon Canvas Laker 301v4 (版图设计系统)

主要优势： 节省一半以上的版图设计时间，并且达到手工版图密度 提供完整的版图设计环境给用户从布局、器件产生、放置、连线、到版图验证及纠错，而在整个环境不需要数据格式的转换。 提供当前最新制成的设计规则来满足超深亚微米（UDSM）以及深亚微米（DFM）的设计要求。 提供器件层级的操作模式替代冗长的、容易产生错误的版图产生及修改模式 基于Shape和格点的绕线功能可应用在全定制版图设计以及自动布局布线版图设计上 通过得到已经被代工厂商鉴定通过的Laker技术文件使客户得到“即插即用”的Laker解决方案 提供电路图驱动版图设计流程（Schematic-Driven Layout），提高使用历史遗留版图以及新建版图设计的效率 主要功能： 整合能力 多接口系统 通过EDIF、Spice 网表导入电路设计或者协同Laker-AMS完成电路驱动版图设计（Schematic-Driven Layout）流程 整合第三方物理验证方案 与Mentor Graphics的Calibre和Synopsys的Hercules紧密整合来显示DRC/LVS结果。可以在Laker环境下使用Calibre或者Hercules做一个或几个模块甚至整个Chip的物理验证 版图布局 全定制版图布局器（Layout Planning） 支持模块面积预估并可以重新设定宽长比例，自动产生PIN位置；提供预先考虑布线拥堵程度的最佳预布局方案。结合虚拟及实际Instance运用置顶以及从底向上的版图设计方式的实现最小冗余空间的版图。 棒状图编辑器(Stick Diagram Compiler) 提供一个高阶的晶体管逻辑抽取方式以实现高效率的晶体管放置，并提供合并、端口交换以及拆分晶体管的编辑功能。 自动晶体管放置（Automatic Transistor Placer） 通过运用链式化、折叠及基于连接关系的放置实现晶体管最佳化摆放达到晶体管摆放自动化。 对称关系产生器（Matching Creator） 利用高级提取对称关系平台自动化地产生定制的对称关系的器件。利用用户预先定义的对称性模式快速产生晶体管放置。 先进器件模型 Magic Cell 集成的深亚微米DRC正确的器件产生器。提供灵活易变的器件模块，实现最有效率的从电路图或网表产生物理器件方式。Magic Cell可以帮助用户大量减少器件准备以及器件维护的工作。最重要的是Magic Cell是目前唯一可以提供手工版图效果并且做到零DRC错误的器件模型。 内置的基于Shape及格点的布线器 Net Router: 自动地产生单条或多条无DRC及LVS错误的连线。 Point to Point Router: 点击源点及目标点来自动化地产生一条无DRC错误的连线。或者利用此功能在交互式模式下自动连线。交互式模式可以设定每一层包括：（1）是否可被用来连线，（2）水平及垂直等级，（3）线宽及线间距 Pathfinder： 交互模式的保证无DRC错误的单条连线产生器。连线方式根据鼠标所在的点，可以认识连线经过区域的同一层并自动绕开。使用快捷键快速地换连线层。 Route by Label: 利用Text或labels作为指引自动地产生多点连线。 层次结构操作（Hierarchy Manipulation）技术 为得到最优化的版图维持在电路图与层次结构优化后版图之间保持层次结构的对应。 重用模块识别（Pattern Recognition）技术 Copy & Associate: 自动在电路数据中搜索并识别与被选择电路结构相同的电路结构。自动复制物理版图并建立正确的连接关系。彻底降低用户建立相同电路版图所花费的多余时间。 Pattern Reuse: 自动在电路数据中搜索并识别与已经实现的物理版图的CELL相同电路结构的电路，即使物理版图已经与电路层次结构不一样也能识别出来。复制并产生相同样式的物理版图而且保持正确的连接信息。彻底降低用户建立相同电路版图所花费的多余时间。 设计期正确（Correct-by-Construction） Rule-Driven Editing: 编辑多边形的同时自动检测、显示并将鼠标吸附至width, space, notch, overlap,以及enclosure等符合设计规则处。通过减少使用标尺及查阅设计规则来提高生产效率。 飞线(Flight Lines) & 即时短路报告(Real-Time Short Detector): 飞线可以指引用户快速而正确的连线。即时短路报告可以在画版图时显示短路错误。这2项功能可以保证作出一个无LVS错误的版图结果。 Push Wire: 当产生path时，push-wire功能可以将相同层的连线推开。 ECO 功能 Laker可以做一个ECO 网表与现成的版图之间的比较，然后在Design Browser窗口中显示出其物理及逻辑上的差异。并可以使用自动化功能修正差异使之修正为符合电路图的版图。 版图纠错与修改（Layout Debugging and Correction） 自动DRC纠正(Auto DRC correction): 根据用户选择区域或Laker DRC 错误显示器自动化修正DRC错误。所有被修正的版图结果将保持原有的连接关系，不会造成新增的LVS错误。此功能支持Laker-iDRC, Calibre以及Hercules等DRC验证工具的错误报告。 Hierarchical Net Tracer: 唯一提供跟踪跨所有层次结构的物理连线的功能。 验证浏览器(Verification Explorer)： 提供与第三方公司的标准版图验证工具的无缝链接，以帮助用户查看并解决DRC错误。 Major Benefits Cuts layout time in half while sustaining important aspects of handcrafted layout density Total system allows user to create layout from floor planning, device creation, placement, wire connection, to layout verification and correction without the need for data translation Supports latest process design rules to meet the physical implementation requirements of Ultra-Deep-Submicron (UDSM) and Design-For-Manufacturing (DFM) Fully customizable bind keys to increase individual productivity and reduce the learning curve for new users Device-level manipulation reduces tedious/error-prone layout creation and editing. Shape and Grid Based routers for both full custom and cell-based design applications Download foundry-certified Laker technology files to instantly use the plug-and-play Laker solution Schematic-Driven Layout Flow works efficiently with legacy and new designs Major Features Integration Capability Versatile System: Import designs from EDIF, Spice netlist, or work with Laker-AMS to perform Schematic-Driven Layout flow. Integration with 3rd party physical verification solutions: Tight link with Mentor Graphics Calibre and Synopsys Hercules for DRC/LVS. Run Calibre or Hercules on one block or the whole chip directly from the Laker menu. Layout Planning Custom Floor Planner: Supports block area estimation with reshaped aspect ratio. Assigns pin locations automatically and provides congestion map information to offer best-practice floor planning scheme. Mixes Soft and Hard Instances to minimize the gap between top-down planning and bottom-up layout realization. Stick Diagram Compiler: Provides a higher level of abstraction enabling more efficient transistor floorplanning, such as gate merging, swapping and splitting. Automatic Transistor Placer: Optimum transistor placement achieved automatically through chaining, folding, and connectivity-based placement. Matching Creator: Customize transistor symmetry using a high level abstraction matching table. Quickly realize transistor placement according to user-defined matching patterns. Advanced Device Model Magic Cell (MCell): Built-in UDSM DRC-correct device generator. Provides flexible device models thus enabling extremely efficient creation of the devices physical layout from circuit components of a netlist or schematic. Magic Cell reduces the effort for device preparation and provides higher levels of device manipulation. Most importantly, Magic Cell is the only device model that has the ability to deliver handcrafted quality and guarantee zero DRC violations. Built-in Shape and Grid Based Router Net Router: Automatically route single or multiple nets, DRC and LVS clean. Point to Point Router: Click on source and target to automatically create a DRC clean route. Or use it in an interactive mode while routing between source and target. Interactive settings for each layer include (1) availability for routing, (2) horizontal and vertical cost functions, and (3) width and space. Pathfinder: Interactive single layer DRC-correct path creator. Router follows the mouse in a point and click mode, recognizing same layers and routing around them. Use bind keys to switch between routing layers. Route by Label: Using text, or labels, as a guide, routes are automatically created between multiple points. Hierarchy Manipulation Capability Manipulate circuit hierarchy on Design Browser or Layout Window in order to optimize layout. Pattern Recognition Technology Copy & Associate: Automatically comb through design database to find matches for selected items. Then automatically copy physical layouts and assign correct connectivity. Drastically reduce time spent on building repeat circuitry. Pattern Reuse: Automatically comb through design database to find matches for cells where the hierarchy of the physical layout does not match that of the original schematic. Copy patterns and create new layouts with correct connectivity. Drastically reduce time spent on building repeat circuitry. Correct-by-Construction Rule-Driven Editing: While editing polygons, automatically check, display, and snap to width, space, notch, overlap, and enclosure rules. Increases productivity by reducing need to use rulers and look up design rules. Flight Lines & Real-Time Short Detector: Flight Lines guide user on where to wire. Real-Time short detector displays short errors as they are created. Both are used to ensure LVS-correct layout results. Push Wire: Create a path where you want, push-wire will move same layer routes out of the way. ECO Capability Laker compares an ECO netlist with the existing layout and then displays physical and/or logical discrepancies in the Design Browser window. Use automated functions to fix the discrepancies and match the layout back to the schematic. Layout Debugging and Correction Auto DRC Correction: Fix DRC violations automatically, based on user selected area or Laker DRC error viewer. All fixed layout results will keep original connections, so as not to introduce additional LVS violations. Supports Laker-iDRC, Calibre, and Hercules DRC verification tool error reports. Hierarchical Net Tracer: Provides a unique feature to trace physical net connectivity through any/all levels of hierarchy. Verification Explorer: Seamless integration with third-party industry standard layout verification tools allows the user to browse and debug DRC errors.